In CCD, CMOS and other types of imagers, field effect transistors such as MOSFETs are employed as part of logic circuitry and DRAM cell region (memory cell region). Conventionally, MOSFETs are fabricated by placing an undoped polycrystalline material, for example polysilicon, over a relatively thin gate oxide, and implanting the polycrystalline material and adjacent active regions with an impurity dopant material to form source and drain regions. If the impurity dopant material for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (“NMOS”) device. Conversely, if the impurity dopant material for forming the source/drain regions is p-type, then the resulting MOSFET is a PMOSFET (“PMOS”) device.
To prevent current leakage and refresh sensitivity from occurring in the source/drain region of an embedded DRAM, the resistance of the polysilicon gate has to be reduced. This reduction in the resistance of the polysilicon gate is typically achieved by forming a silicide layer, such as a tungsten silicide layer, on the polysilicon gate to improve the conductivity of the gate. Although the formation of a silicide layer on the polysilicon gate is highly desirable for embedded DRAMs, the silicide layers pose some drawbacks that need to be overcome.
To better illustrate the drawbacks as a result of silicide formation for reducing the resistance of the polysilicon gate, reference is now made to FIG. 1, which is a schematic cross-sectional view of an embedded DRAM having a memory cell region 20a formed in memory region A of the substrate 10, and a logic circuitry 20b formed in logic region B of the substrate 10.
The structures of FIG. 1 are formed by providing a gate oxide layer 12 and an undoped polysilicon layer on the substrate 10. Subsequent to the formation of undoped polysilicon layer, P-type and N-type ions are respectively implanted into the undoped polysilicon layer by using an implanting mask to form a doped polysilicon layer 13. A silicide layer 14, for example a tungsten silicide layer 14, is formed on the doped polysilicon layer 13 to improve the conductivity of the gate formed in subsequent processes. The tungsten silicide layer 14, doped polysilicon layer 13 and gate oxide layer 12 are patterned to form dual gate structures 16a, 16b each having respective N+ polysilicon layer 13a and P+ polysilicon layer 13b. Spacers 15 are formed on the sidewalls of the dual gate structure 16a and 16b. The substrate 10 underneath the dual gate structure 16a and gate structure 16b has source/drain regions 17a, 17b formed therein. The source/drain regions 17a, 17b are formed by implanting ions into the substrate 10. Ions in the source/drain regions 17a, 17b need to be activated thermally or by rapid thermal process (RTP).
As noted above, the formation of the tungsten silicide 14 is desirable as it increases the conductivity of the polysilicon layer 13a, 13b. In some IC circuit, NMOS and PMOS are directly connected to each other. However, due to the high backend thermal budget and because the diffusion coefficient of impurities in the tungsten silicide layer 14 is much larger than that in the polysilicon layer 13a, 13b, N-type ions (typically phosphorus) in the polysilicon layer 13a of the dual gate 16a diffuse into the P-type polysilicon layer 13b. Similarly, P-type ions (typically boron) in the polysilicon layer 13b of the dual gate 16b diffuse into the N-type polysilicon layer 13a. Therefore, interdiffusion 19 as seen in FIG. 1 is caused between the polysilicon layers 13a, 13b of the dual gate. In addition, P-type ions (typically boron) in the polysilicon layer 13b also diffuse into the semiconductor substrate 10 (typically silicon). This migration of impurity boron/phosphorus atoms at the source/drain interface and the diffusion of boron atoms into the silicon substrate decreases the “refresh time” of the DRAM device, and consequently increases the DRAM error rate. The “refresh time” of a DRAM cell is defined as the length of time over which the DRAM cell can retain a sufficient amount of charge for its intended data state to be determined by a sense amplifier circuit. Before this period of time expires, the DRAM cell must be reprogrammed or “refreshed” and, consequently, it is desirable that the refresh time between the refresh operations be as long as possible.
The above-noted migration and cross-contamination of impurity boron/phosphorus atoms is further exacerbated by the high temperature processes for the formation of capacitors which are employed in conjunction with other device components for charge storage and/or in analog signal processing circuits. In some IC designs, the formation of these capacitors requires deposition of another layer of polysilicon (employed as capacitor electrode layer) subsequent to the formation of the silicide layer described above. The subsequent formation of this polysilicon layer typically requires a high temperature process of about 750° C. to about 800° C. As a result of these high temperature requirements for the capacitor formation, the P-type ions (typically boron) further diffuse into the silicon substrate and from the P-type polysilicon layer 13b into the N-type polysilicon layer 13a, which in turn makes the N-type polysilicon layer 13a more like the P-type polysilicon layer 13b. 
The above-noted migration and cross-contamination are further encountered when designing various integrated circuits that include diverse components such as transistors and capacitors. For example, an imager IC may include an array of pixels, each including a capacitive elements that stores photogenerated charge and readout circuitry to provide a readout signal indicating the level of stored charge. The readout circuitry typically includes several transistors, and the imager IC may also have peripheral circuitry that also includes capacitive elements and transistors. Each component, whether a capacitor or a transistor, may include one or more conductive layers and a silicide layer formed over the conductive layer, to reduce resistance.
Accordingly, there is a need for an improved method for preventing the migration of impurity atoms into the active regions of a DRAM device, as well as a method for increasing the refresh time and reducing the error rate of such DRAM devices. There is also a need for the formation of a silicide layer that would prevent the occurrence of the above-mentioned problems. An optimized process for the formation of improved imagers and imaging devices having array and periphery area transistors and capacitors with improved characteristics is also needed.